1. Field of the Invention
The present invention relates generally to the field of integrated circuit devices. More particularly, the present invention relates to the field of error detection for integrated circuit devices.
2. Description of Related Art
Integrated circuit devices such as microprocessors, memory controllers, input/output controllers, etc., typically encounter various device and data error conditions in performing their functions. Such devices record detected error conditions by setting a corresponding bit in an error status register within the device. The location of the bit within the error status register corresponds to the error condition detected. Exemplary error conditions include hardware failures, parity errors, single-bit and multiple-bit error correcting code (ECC) errors, communication protocol violations, etc. Error handling may be performed by reading the error status register to identify any detected error conditions and performing suitable techniques to contain an error condition, possibly recover from the error condition, and/or reset the device.
An error condition associated with an integrated circuit device function is detected. Whether the detected error condition is a first detected error condition is determined, and, if so, the detected error condition is identified as the first detected error condition.